The obvious choice is to use much faster acting solid state electronic switches which use metal oxide semiconductor (MOS) analogue gates to route the signal currents from their input to their output, with the well-known CMOS 4016B bilateral switch being the most common example. The switching and routing of digital and analogue signals (both voltage and current) can easily be done using mechanical relays and their contacts, but these can be slow and costly. The open and closed operations of the switch positions are usually controlled by some digital logic network, with standard analogue switches available in many styles and configurations that we can use as a transmission gate.įor example, single or dual normally open (NO) or normally closed (NC), single-pole single-throw (SPST), single-pole, double-throw (SPDT) configurations etc, in much the same way as for conventional electromechanical relays and contacts. My entire lab 4 Cadence directory can be found in Lab_4.The analogue switch is a solid-state semiconductor switch that controls the transmission path of analogue signals. So once again, the layout is extracted and we perform the LVS to ensure that the net-lists match: Once this is done, we can perform the LVS test with We use the schematic from Tutorial 2, and add 4 bond pads given in the Through vias to the metal 1 of the device, and also its The 4 terminals of the device to 4 probe pads, and ensure itĬloseup of the PMOS layout shows how the metal 3 wires are connected Theĭimensions of the device are 12u (length) by. Now, for the PMOS device, the same procedure is repeated. Theįollowing image shows the extracted view of the layout along with the The schematic is then constructed, with 4 probe pads connected to the 4 terminals of the NMOS device:įinally, after extracting the layout, we perform the LVS check. Measurements and connection to the metal 3 wires which go to the probe The following image shows a closeup of the NMOS device, detailing its Shows the entire layout and that it DRCs with no errors: Theĭevice is connected to 4 probe pads and DRC the layout the image below Part 2 - Layout of a 6u/600nm NMOS device and 12u/600nm PMOS device connected to 4 probe pads:Ī) The layout of a 6u/600nm NMOS device. The setup only requires a dc analysis, sweeping VSG from 0 to 2V in 1mV steps: Linear steps in the Parametric Analysis window:Ĥ) Fourthly and finally for this part of the lab, we use the same PMOS transistor schematic to simulate the ID vs. The dc analysis window, and then we let VSG vary from 0 to 5 in 1V We add the Variable VSG with a value of 1 (whichĭoesn't matter), set VSD (V1 on the schematic) to go from 0 to 5V in We again set up the parameters again, similar to what we did with the The schematic is as follows, with the body connected to vdd! here, which is VSD. VSD (not VDS, as in the NMOS device) curve. VGS curve, we can just choose the dc analysis and sweep the V0 parameter from 0 to 2V in 1mV steps:ģ) Thirdly, we want to make a schematic of a 12u/600n (L/W) PMOS transistor, to simulate the ID vs. The green arrow in the Parametric Analysis window to run the analysis.įinally, we get the following simulation results:Ģ) The second schematic is the same, but this time we hold VDS constant and vary only VGS. Finally, we select Tools -> Parametric Analysis andĬhange VGS from 0 to 5V with Linear Steps of step size 1. ![]() Which can be selected on the schematic by clicking on the top node of Also, we must ensure that we are plotting the current ID, (VGS is going to vary, so this valueĬould be anything.) Next, we select Analysis -> Choose, select theĭc analysis, and sweep the component V1 (which is our VDS) from 0 to 5V Then adding a new variable, VGS, from the tab Variables -> Edit andĪdding VGS with a value of 2. The simulation parameters must be set up, first by loading a new state, Source, VDS (V1 on the schematic), has a value of 0 so we can sweep it Voltage source on the left, V0, has a value of VGS, while the other We need toĮnsure the body of the NMOS device is connected to ground, and that the The schematic was drafted, using the nmos4 transistor. VDS curve of a 6u/600n (L/W) NMOS device, for VGS varying from 0 to 5V in 1V steps while VDS varies from 0 to 4V in 1mV steps. Part 1 - Generating schematics for simulations of IV characteristics for NMOS and PMOS transistors:ġ) This first schematic is for simulating the ID vs. NMOS and PMOS transistors, as well as how to construct the layout of
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